SACHEM To Present Technical Paper on Improved Silicon Etching for Sub-65nm Devices

New technology for planar-selective crystalline silicon etch delivers increased advantages.
Austin, TX – February 18, 2008 – SACHEM, Inc. announced today that an advanced technology paper will be delivered at the Semiconductor International Wafer Cleaning Seminar in Tokyo. The one-day technical seminar will focus on new challenges and technologies in wafer cleaning. The seminar is scheduled for Friday, February 22nd in the Tokyo Station Conference Center in Tokyo, Japan.
SACHEM has designed new technology for planar-selective crystalline silicon etching. The technical paper will be delivered by Russell Stevens, SACHEM’s Manager of New Business Development for Electronic Materials. In addition to a discussion of the history and limitations of silicon etching, Mr. Stevens will highlight new and technically challenging applications for silicon etch.
One such challenging application is the requirement to etch crystalline silicon with planar selectivity to create complex Silicon Germanium (SiGe) source-drain recess structures in pMOS devices. Creation of the sigma-shaped source and drain recesses is advantageous for achieving maximum strain in the transistor. Mr. Stevens will describe the capabilities of existing etchants, as well as SACHEM’s new SelectEtch™ SE-1430 silicon etchant. The new SE-1430 etchant offers a significant increase over Potassium Hydroxide in the selectivity between crystal planes.
SACHEM invites interested engineers and scientists to attend the seminar. Additional discussions regarding advanced FEOL selective etching can be held during the seminar or in the near future.